A hard short circuit arising in an inverter power circuit will cause the IGBT collector current to rise to abnormally high levels which results in the IGBT pulling out of the normal saturated condition.
Commercially available gate drive optocoupler ICs with desaturation (desat) detection and soft turn-off capability, such as the Avago ACPL331J, HCPL-316J and Renesas PS9402, have the disadvantage of an internally fixed threshold level for the Desat input which can be as low as 6.0V in some designs.
FIG. 1 shows a known optocoupler gate drive product with desaturation fault detection, the Avago ACPL-331J 10. The Avago ACPL-331J has a soft turn-off feature. The DESAT pin (pin 14) of the optocoupler 10 monitors the collector-emitter voltage Vce of an IGBT 20. When there is a short circuit and a very high current flow through the IGBT 20, the IGBT will go into desaturation mode and the collector-emitter voltage Vce of the IGBT will rise. A fault is detected by the optocoupler gate drive 10 once the voltage Vce goes above the internal desaturation fault detection threshold voltage of the IC. When a fault is detected by the DESAT pin (pin 14), a weak pull-down device in the output drive stage will turn on to “softly” turn off the IGBT and so prevent large di/dt induced voltages.
In a conventional design as shown in FIG. 1, diodes D1 and D2 (known as Vce sense diodes or DESAT diodes) are connected directly to the Desat input (pin 14) of the IC 10 via a resistor R2 which would have a typical/recommended value of 100Ω. A blanking time filter is defined by R1 and C1, typical values being 1 k to 4.7 kΩ and 1 n to 4.7 nF respectively to give a blanking time in the order of several microseconds. In some schemes C1 may be set as low as 100 pF and R1 omitted but this approach may lead to noise immunity issues in the design.
VE is the common voltage (e.g. nominally 0V) for the supply rails GD_V+ and GD_V−, and the VE connection to the IC (pin 16) connects to the emitter E of the IGBT 20.
A typical Vce saturation voltage, Vce sat, for an IGBT module operating at for example between 1.5 and 2 times rated current and at maximum rated operating temperature may exceed 3V. The saturation voltage may be higher if production spreads and internal voltage drops due to the module construction are taken into account.
The design headroom for the Desat input may be calculated as follows:
                              i          D                =                                            V              OH                        -                          (                                                V                                      D                    ⁢                                                                                  ⁢                    1                                                  +                                  V                                      D                    ⁢                                                                                  ⁢                    2                                                  +                                  V                  CE_sat                                            )                                                          R              ⁢                                                          ⁢              1                        +                          R              ⁢                                                          ⁢              2                                                          (        1        )            
VOH is the output high voltage of the IC 10. VD1 (and VD2) is the on-state forward voltage of desaturation (DESAT) diode D1 (and second desaturation diode D2 if provided). These diodes are typically chosen to have a reverse voltage rating of at least 1000V however their forward voltage rating is often typically higher than a standard low voltage device. The desaturation diode may comprise one or more diodes. A string of DESAT diodes may be provided in series or a single DESAT diode may be provided.
If the IC output high voltage, VOH, is 15V, the VCE—sat voltage is 3V and R1 is chosen to be 1 kΩ, the design headroom for the Desat input may be calculated as follows:
      i    D    =                    15        -                  (                      0.8            +            0.8            +            3.0                    )                            1000        +        100              =          9.45      ⁢                          ⁢      mA      
The desaturation voltage VDESAT may then be calculated as follows:VDESAT=VOH−R1×ID  (2)VDESAT=15−1k×9.45=5.55V VDesat—Headroom=VDESAT—Threshold—Min−VDESAT  (3)
where VDESAT—Threshold—Min is the minimum internal threshold level fixed internally within the ICVDesat—Headroom=6−5.55=0.45V 
From these calculations, the design headroom is shown to be less than 0.5V, or even lower if the maximum Vce sat for the IGBT under consideration is taken as high as 3.5V. This could lead to nuisance tripping of the IC and be a reliability issue to the inverter power circuit design.
Generally, a workable design value for the Vce threshold would be between 7 to 13V.
When the conventional circuit shown in FIG. 1 is implemented in a practical design some additional precautions may also be taken. For instance, the reverse recovery of the IGBT anti-parallel free wheel diode 30 can cause the Desat pin to be pulled transiently below ground (below the potential at VE) and therefore forward bias the substrate diode of the IC. This affect could result in a false Fault signal being generated at pin 3 of the IC signal.
To minimize the disturbances, the design value of C1 needs to be considered carefully by balancing the requirements of noise suppression and blanking time.
Additionally, the Vce sense diodes D1 and D2 need to be fast recovery and have a small reverse capacitance to minimize the disturbance on the IC. A schottky diode D3 may be connected between the Desat pin (pin 14) and VE (pin 16) to prevent the forward biasing of the substrate diode from power circuit switching transients.
A zener diode D4 with a clamping value of around 8V may also be connected in parallel with D3 to prevent positive transients from affecting the Desat pin (pin 14).
The anti-parallel freewheel diode 30 can have a large instantaneous forward voltage transient which will exceed the normal forward voltage rating of the diode. This may present a negative transient at the Desat input (pin 14) which can cause current to be drawn out of the IC. To limit the current drawn, a resistor R2 is provided in series with D1 and D2, with a typical value of around 100 Ω.